An IGFET is a semiconductor device in which a gate dielectric layer electrically insulates a gate electrode from a channel zone extending between a source zone and a drain zone. The channel zone in an enhancement-mode IGFET is part of a body region, often termed the substrate or substrate region, that forms respective pn junctions with the source and drain. In an enhancement-mode IGFET, the channel zone consists of all the semiconductor material between the source and drain. During IGFET operation, charge carriers move from the source to the drain through a channel induced in the channel zone along the upper semiconductor surface. The threshold voltage is the value of the gate-to-source voltage at which the IGFET switches between its on and off states for given definitions of the on and off states. The channel length is the distance between the source and drain along the upper semiconductor surface.
IGFETs are employed in integrated circuits (“ICs”) to perform various digital and analog functions. As IC operational capabilities have advanced over the years, IGFETs have become progressively smaller, leading to a progressive decrease in minimum channel length. An IGFET that operates in the way prescribed by the classical model for an IGFET is often characterized as a “long-channel” device. An IGFET is described as a “short-channel” device when the channel length is reduced to such an extent that the IGFET's behavior deviates significantly from the classical IGFET model. Although both short-channel and long-channel IGFETs are employed in ICs, the great majority of ICs utilized for digital functions in very large scale integration applications are laid out to have the smallest channel length reliably producible with available lithographic technology.
A depletion region extends along the junction between the source and the body region. Another depletion region extends along the junction between the drain and the body region. A high electric field is present in each depletion region. Under certain conditions, especially when the channel length is small, the drain depletion region can laterally extend to the source depletion region and merge with it below the upper semiconductor surface. This phenomenon is termed (bulk) punchthrough. When punchthrough occurs, the operation of the IGFET cannot be controlled with its gate electrode. Punchthrough needs to be avoided.
Various techniques have been employed to improve the performance of IGFETs, including those operating in the short-channel regime, as IGFET dimensions have decreased. One performance improvement technique involves providing an IGFET with a two-part drain for reducing hot-carrier injection. The IGFET is also commonly provided with a similarly configured two-part source.
FIG. 1 illustrates such a conventional long n-channel IGFET 20 as described in U.S. Pat. No. 6,548,842 B1 (Bulucea et al.). The upper surface of IGFET 20 is provided with recessed electrically insulating field-insulating region 22 that laterally surrounds active semiconductor island 24 having n-type source/drain (“S/D”) zones 26 and 28. Each S/D zone 26 or 28 consists of very heavily doped main portion 26M or 28M and more lightly doped, but still heavily doped, lateral extension 26E or 28E.
S/D zones 26 and 28 are separated from each other by channel zone 30 of p-type body material 32 consisting of lightly doped lower portion 34, heavily doped intermediate well portion 36, and upper portion 38. Although most of upper body-material portion 38 is moderately doped, portion 38 includes ion-implanted heavily doped halo pocket portions 40 and 42 that respectively extend along S/D zones 26 and 28. IGFET 20 further includes gate dielectric layer 44, overlying gate electrode 46, electrically insulating gate sidewall spacers 48 and 50, and metal silicide layers 52, 54, and 56.
S/D zones 26 and 28 are largely mirror images of each other. Halo pocket portions 40 and 42 are also largely mirror images of each other so that channel zone 30 is symmetrically longitudinally graded with respect to channel dopant concentration. As a result, IGFET 20 is a symmetric device. Either S/D zone 26 or 28 can act as source during IGFET operation while the other S/D zone 28 or 26 acts as drain. This is especially suitable for digital situations where S/D zones 26 and 28 respectively function as source and drain during certain time periods and respectively as drain and source during other time periods.
FIG. 2 illustrates how net dopant concentration NN varies as a function of longitudinal distance x for IGFET 20. Since IGFET 20 is a symmetric device, FIG. 2 presents only a half profile starting from the channel center. Curve segments 26M*, 26E*, 28M*, 28E*, 30*, 40*, and 42* in FIG. 2 respectively represent the net dopant concentrations of regions 26M, 26E, 28M, 28E, 30, 40, and 42. Dotted curve segment 40″ or 42″ indicates the total concentration of the p-type dopant that forms halo pocket 40 or 42, including the p-type dopant introduced into the location for S/D zone 26 or 28 in the course of forming pocket 40 or 42.
In addition to helping alleviate undesired roll off of the threshold voltage at short channel length, the presence of halo pockets 40 and 42 in IGFET 20 causes the net p-type dopant concentration in channel zone 30 to be increased along each S/D zone 26 or 28, specifically along each lateral extension 26E or 28E. The onset of punchthrough is thereby alleviated because the thickness of the channel-zone portion of the depletion region extending along the junction of source-acting S/D zone 26 or 28 is reduced.
Body material 30 is provided with an additional doping characteristic to further alleviate punchthrough. Based on the information presented in U.S. Pat. No. 6,548,842 B1, FIG. 3a roughly depicts how absolute concentrations NT of the p-type and n-type dopants vary as a function of depth y along a vertical line extending through main S/D portion 26M or 28M as a result of the additional doping characteristic. Curve segment 26M″ or 28M″ in FIG. 3a represent the total concentration of the n-type dopant that defines main S/D portion 26M or 28M. Curve segments 34″, 36″, 38″, 40″, and 42″ together represent the total concentration of the p-type dopant that defines respective regions 34, 36, 38, 40, and 42.
The additional doping characteristic is achieved by ion implanting p-type upper body-material portion 38 with p-type anti-punchthrough (“APT”) dopant that reaches a maximum concentration at a depth more than 0.1 μm below the upper semiconductor surface but no more than 0.4 μm below the upper surface. For the situation represented in FIG. 3a where main S/D portions 26M and 28M extend approximately 0.2 μm below the upper surface, the p-type APT dopant reaches a maximum concentration at a depth of approximately 0.2 μm. By locating the p-type APT dopant in this manner, the thickness of the channel-zone portion of the depletion region extending along the pn junction of source-acting S/D zone 26 or 28 is further reduced so as to further alleviate punchthrough.
Well region 36 is defined by ion implanting IGFET 20 with p-type well dopant that reaches a maximum concentration at a depth below that of the maximum concentration of the p-type APT dopant. Although, the maximum concentration of the p-type well dopant is somewhat greater than the maximum concentration of the p-type APT dopant, the vertical profile of the total p-type dopant is relatively flat from the location of the maximum well-dopant concentration up to main S/D portion 26M or 28M. In particular, NT concentration of the total p-type dopant decreases by considerably less than a factor of 5 in going from the location of the maximum well-dopant concentration up to main S/D portion 26M or 28M.
U.S. Pat. No. 6,548,842 B1 discloses that the p-type dopant profile along the above-mentioned vertical line through main S/D portion 26M or 28M can be further flattened by implanting an additional p-type dopant that reaches a maximum concentration at a depth between the depths of the maximum concentrations of APT and well dopants. This situation is illustrated in FIG. 3b for such a variation of IGFET 20 where curve segment 58″ indicates the variation caused by the further p-type dopant. In FIG. 3b, the maximum concentration of the further p-type dopant lies between the maximum concentrations of the APT and well dopants. Accordingly, concentration NT of the total p-type dopant again decreases by considerably less than a factor of 5 in moving from the location of the maximum well-dopant concentration to portion 26M or 28M.
A symmetric IGFET structure is not needed in situations, especially many analog applications, where current flows in only one direction through an IGFET during device operation. As further discussed in U.S. Pat. No. 6,548,842 B1, the halo pocket portion can be deleted from the drain side. IGFET 20 thereby becomes long n-channel IGFET 60 as shown in FIG. 4a. IGFET 60 is an asymmetric device because channel zone 30 is asymmetrically longitudinally dopant graded. S/D zones 26 and 28 in IGFET 60 respectively function as source and drain. FIG. 4b illustrates asymmetric short n-channel IGFET 70 corresponding to long-channel IGFET 60. In IGFET 70, source-side halo pocket 40 closely approaches drain 28. Net dopant concentration NN as a function of longitudinal distance x along the upper semiconductor surface is shown in FIGS. 5a and 5b respectively for IGFETs 60 and 70.
Asymmetric IGFETs 60 and 70 receive the same APT and well implants as symmetric IGFET 20. Along vertical lines extending through source 26 and drain 28, IGFETs 60 and 70 thus have the dopant distributions shown in FIG. 3a except that dashed-line curve segment 62″ represents the vertical dopant distribution through drain 28 due to the absence of halo pocket 42. When the IGFET structure is provided with the additional well implant to further flatten the vertical dopant profile, FIG. 3b presents the consequent vertical dopant distributions again subject to curve segment 62″ representing the dopant distribution through drain 28.
U.S. Pat. Nos. 6,078,082 and 6,127,700 (both Bulucea) describe IGFETs having asymmetric channel zones but different vertical dopant characteristics than those employed in the inventive IGFETs of U.S. Pat. No. 6,548,842 B1. IGFETs having asymmetric channel zones are also examined in other prior art documents such as (a) Buti et al., “Asymmetrical Halo Source GOLD drain (HS-GOLD) Deep Sub-half Micron n-MOSFET Design for Reliability and Performance”, IEDM Tech. Dig., 3-6 December 1989, pp. 26.2.1-26.2.4, (b) Chai et al., “A Cost-Effective 0.25 μm Leff BiCMOS Technology Featuring Graded-Channel CMOS (GCMOS) and a Quasi-Self-Aligned (QSA) NPN for RF Wireless Applications”, Procs. 2000 Bipolar/BiCMOS Circs. and Tech. Meeting, 24-26 September 2000, pp. 110-113, (c) Cheng et al., “Channel Engineering for High Speed Sub-1.0 V Power Supply Deep Submicron CMOS”, 1999 Symp. VLSI Tech., Dig. Tech. Paps., 14-16 June 1999, pp. 69 and 70, (d) Deshpande et al., “Channel Engineering for Analog Device Design in Deep Submicron CMOS Technology for System on Chip Applications”, IEEE Trans. Elec. Devs., September 2002, pp. 1558-1565, (e) Hiroki, “A High Performance 0.1 μm MOSFET with Asymmetric Channel Profile”, IEDM Tech. Dig., December 1995, pp. 17.7.1-17.7.4, (f) Lamey et al., “Improving Manufacturability of an RF Graded Channel CMOS Process for Wireless Applications”, SPIE Conf. Microelec. Dev. Tech. II, September 1998, pp. 147-155, (g) Ma et al., “Graded-Channel MOSFET (GCMOSFET) for High Performance, Low Voltage DSP Applications”, IEEE Trans. VLSI Systs. Dig., December 1997, pp. 352-358, (h) Matsuki et al., “Laterally-Doped Channel (LDC) Structure for Sub-Quarter Micron MOSFETs”, 1991 Symp. VLSI Tech., Dig. Tech. Paps., 28-30 May 1991, pp. 113 and 114, and (i) Su et al., “A High-Performance Scalable Submicron MOSFET for Mixed Analog/Digital Applications”, IEDM Tech. Dig., December 1991, pp. 367-370.
The term “mixed signal” refers to ICs containing both digital and analog circuitry blocks. The digital circuitry typically employs the most aggressively scaled n-channel and p-channel IGFETs for obtaining the maximum potential digital speed at given current leakage specifications. The analog circuitry utilizes IGFETs and/or bipolar transistors subjected to different performance requirements than the digital IGFETs. Requirements for the analog IGFETs commonly include high linear voltage gain, good small-signal and large-signal frequency response at high frequency, good parameter matching, low input noise, well controlled electrical parameters for active and passive components, and reduced parasitics, especially reduced parasitic capacitances. Although it would be economically attractive to utilize the same transistors for the analog and digital blocks, doing so would typically lead to weakened analog performance. Many requirements imposed on analog IGFET performance conflict with the results of digital scaling.
More particularly, the electrical parameters of analog IGFETs are subjected to more rigorous specifications than the IGFETs in digital blocks. In an analog IGFET used as an amplifier, the output resistance of the IGFET needs to be maximized in order to maximize its intrinsic gain. The output resistance is also important in setting the high-frequency performance of an analog IGFET. In contrast, the output resistance is considerably less importance in digital circuitry. Reduced values of output resistance in digital circuitry can be tolerated in exchange for higher current drive and consequent higher digital switching speed as long as the digital circuitry can distinguish its logic states, e.g., logical “0” and logical “1”.
The shapes of the electrical signals passing through analog transistors are critical to circuit performance and normally have to be maintained as free of harmonic distortions and noise as reasonably possible. Harmonic distortions are caused primarily by non-linearity of transistor gain and transistor capacitances. Hence, linearity demands on analog transistors are very high. The parasitic capacitances at pn junctions have inherent voltage non-linearities that need to be alleviated in analog blocks. Conversely, signal linearity is normally of secondary importance in digital circuitry.
The small-signal analog speed performance of IGFETs used in analog amplifiers is determined at the small-signal frequency limit and involves the small-signal gain and the parasitic capacitances along the pn junctions for the source and drain. The large-signal analog speed performance of analog amplifier IGFETS is similarly determined at the large-signal frequency limit and involves the non-linearities of the IGFET characteristics.
The digital speed of logic gates is defined in terms of the large-signal switching time of the transistor/load combination, thereby involving the drive current and output capacitance. Hence, analog speed performance is determined differently than digital speed performance. Optimizations for analog and digital speeds can be different, leading to different transistor parameter requirements.
Digital circuitry blocks predominantly use the smallest IGFETs that can be fabricated. Because the resultant dimensional spreads are inherently large, parameter matching in digital circuitry is often relatively poor. In contrast, good parameter matching is usually needed in analog circuitry to achieve the requisite performance. This typically requires that analog transistors be fabricated at greater dimensions than digital IGFETs subject to making analog IGFETS as short as possible in order to have source-to-drain propagation delay as low as possible.
In view of the preceding considerations, it is desirable to have a semiconductor architecture that provides IGFETs with good analog characteristics. The analog IGFETs should have high intrinsic gain, high output resistance, high small-signal speed with reduced parasitic capacitances, especially reduced parasitic capacitances along the source and drain junctions. It is also desirable that the architecture be capable of providing high-performance digital IGFETs.